4 16 decoder using two 3-8 decoders pdf

Homework equations the attempt at a solution truth table. The device can be used as a 1to 16 demultiplexer by. Binary decoders are another type of digital logic device that has inputs of 2bit, 3bit or 4bit. Design of lowpower, area efficient 2 4 and 4 16 mixedlogic line decoders. Homework statement how to design a 2 to 4 decoder using 4 to 16 decoder. The 238 can be used as an eight output demultiplexer by using one of the active.

Here is what i did, note that i couldnt continue writing the full table. The 2 4low power decoder and 2 4 low power inverting decoder schematics are shown in fig. Design of low power, high performance 24 and 416 mixed. Here a much larger 4 3 data plus 1 enable to 16 line binary decoder has been implemented using two smaller 3to8 decoders. The device features two input enable e0 and e1 inputs. How can i design a 4to16 decoder using two 3to8 decoders and. Circuit design of 4 to 16 decoder using 3 to 8 decoder. A decoder circuit of the higher combination is obtained by adding two or more lower combinational circuits.

Design a 2 to 4 decoder using 4 to 16 decoder physics forums. A high on either of the input enables forces the outputs high. For the two decoders out there given the same input with enables inverted,this simply means one of 3 to 8 decoder will be provided with a enable and the other will. How to design a 4 to 16 decoder using 3 to 8 decoder elprocus. A vhdl program for 64 to 1 multiplexer using four 4 to 1 multiplexers is not possible, as four 4 to 1 multiplexers provide only 16 inputs, only 1 4 of what is needed. One of these outputs will be active high based on the comb. Digital circuits decoders decoder is a combinational circuit that has. So ill use all three of the first and the first of the second, and connect the last two inputs to ground, since they wont be used. Answer to design a 4 to 16 line decoder using two 3to8 line decoders and 16 2 input and gate. When enable pin is high at one 3 to 8 decoder circuits then it. Two activelow and one activehigh enable inputs reduce the need for external gates or inverters. An example of a 2to4 line decoder along with its truth table is given as.

It decodes four binary weighted address inputs a0 to a3 to sixteen mutually exclusive outputs y0 to y15. What i did, i used 2x of 2 to 4 decoder and 1x 3to8 decoder. When two 3 to 8 decoder circuits are combined the enable pin acts as the input for both the decoders. You would need to connect first 3 data lines in parellel to the two decoder ics, then use the remaining high bit as an enable to the. Used to activate exactly one of 2n outputs based on nbit. Design a 4 to 16 line decoder using two 3to8 line decoders and 16 2 input and gate. How to build a 4x16 decoder using 3x8 decoders duration. Any pointers on where to go from here are appreciated. How to design a 4 to 16 decoder using 3 to 8 decoder. Since i am using two 38 decoders to develop a 4 to 16 decoder, i want to use 4 inputs out of the two 38 decoders.